1. Field of the Invention
The present invention generally relates to a semiconductor device, and more specifically, it relates to a semiconductor device which has a multilayer interconnection structure. The present invention also relates to a method of fabricating such a semiconductor device.
2. Description of the Background Art
FIG. 12 is a sectional view showing a conventional semiconductor device having a multilayer interconnection structure.
Field oxide films 7 are formed on a major surface of a silicon substrate 1, and gate electrode wires 6 are provided on the field oxide films 7. A first interlayer insulating film 8 is formed on the silicon substrate 1, to cover the gate electrode wires 6. Patterns 9a, 9b and 9c of a first aluminum interconnection layer are formed on the first interlayer insulating film 8. A second interlayer insulating film 10 is provided to cover the patterns 9a, 9b and 9c of the first aluminum interconnection layer. The second interlayer insulating film 10 is provided therein with first and second via holes 10a and 10b for exposing first and second coupling portions 90a and 90b of the patterns 9a and 9b of the first aluminum interconnection layer respectively. A second aluminum interconnection layer 12 is provided to be connected with the first and second coupling portions 90a and 90b through the first and second via holes 10a and 10b respectively. A passivation film 13 is provided over the silicon substrate 1, to cover the second aluminum interconnection layer 12.
A method of fabricating the conventional semiconductor device shown in FIG. 12 is now described.
FIGS. 13 to 17 are sectional views showing steps in the method of fabricating the conventional semiconductor device in due order.
Referring to FIG. 13, field oxide films 7 are formed on a major surface of a silicon substrate 1, and then gate electrode wires 6 are formed on the field oxide films 7. A first interlayer insulating film 8 is formed on the silicon substrate 1, to cover the gate electrode wires 6. Patterns 9a, 9b and 9c of a first aluminum interconnection layer are formed on the first interlayer insulating film 8, and a second interlayer insulating film 10 is formed to cover these patterns 9a, 9b and 9c. The second interlayer insulating film 10 is obtained by forming a silicon oxide film over the silicon substrate 1 by plasma CVD, then forming an inorganic coating/insulating film thereon by rotation coating, and thereafter etching back these films by dry etching. The inorganic coating/insulating film is prepared from a spin-on glass film (SOG film).
Referring to FIG. 14, a resist film 22 is applied onto the second interlayer insulating film 10. Then the resist film 22 is so patterned as to define first and second openings 22a and 22b in regions to be provided with first and second via holes for exposing first and second coupling portions of the patterns 9a and 9b of the first aluminum interconnection layer respectively.
Referring to FIG. 15, the patterned resist film 22 is used as a mask to selectively etch the second interlayer insulating film 10 by reactive ion etching, for example, thereby forming first and second via holes 10a and 10b. Thereafter the resist film 22 is removed by oxygen plasma or the like, as shown in FIGS. 15 and 16.
Referring to FIG. 17, an aluminum film is formed entirely over the surface of the second interlayer insulating film 10 by sputtering, for example, to fill up the first and second via holes 10a and 10b. Thereafter this aluminum film is patterned by photolithography and reactive ion etching, thereby forming patterns of a second aluminum interconnection layer 12. A silicon nitride film for defining a passivation film 13 is formed entirely over the surface of the silicon substrate 1 by plasma CVD, to cover the patterns of the second aluminum interconnection layer 12. Thereafter openings (not shown) are formed in the passivation film 13 for exposing bonding pads, which in turn are connected with bonding wires to complete the steps of fabricating the semiconductor device.
In the aforementioned conventional method of fabricating a semiconductor device having a multilayer interconnection structure, however, the following problem has remarkably arisen with layer multiplication and refinement of the interconnection structure:
Due to refinement of the interconnection structure, i.e., reduction of the interconnection width, it is necessary to reduce via holes in diameter. Consequently, it is difficult to form patterns for the via holes. This problem is now described in more detail with reference to FIG. 18. Referring to FIG. 18, a resist film 22 is provided therein with first and second openings 22a and 22b for defining two via holes. The first and second openings 22a and 22b are adapted to define first and second via holes for exposing coupling portions of patterns 9a and 9b of a first aluminum interconnection layer respectively.
The first opening 22a is formed in a region for defining the first via hole, i.e., a portion where a field oxide film 7, a gate electrode wire 6a and the pattern 9a of the first aluminum interconnection layer are overlapped with each other. On the other hand, the second opening 22b is formed on a region which is provided with only the pattern 9b of the first aluminum interconnection layer. In other words, the first opening 22a is formed on a projecting portion of an interlayer insulating film 10, while the second opening 22b is formed on a depressed portion thereof. Namely, a distance a.sub.3 is greater than a distance b.sub.3 in FIG. 18.
When the resist film 22 is applied onto the interlayer insulating film 10 containing such a step, its thickness is relatively reduced on the projecting portion and relatively increased on the depressed portion. In other words, a distance a.sub.4 is less than a distance b.sub.4 in FIG. 18. If the resist film 22 is patterned by photolithography in such a state, a diameter a.sub.2 is inevitably greater than a diameter b.sub.2 in FIG. 18 at the bottoms of the resist patterns, although a diameter a.sub.1 is equal to a diameter b.sub.1 at the tops thereof.
The reason for this is now described with reference to FIGS. 19, 20 and 21.
FIG. 19 illustrates optimum focal positions of respective portions in a resist film 22 being formed on an interlayer insulating film 10 which has a step. Symbols a and b denote the optimum focal positions of portions A and B of the resist film 22 having small and large thicknesses respectively. When the respective portions A and B are brought into focus to expose the resist film 22, it is possible to obtain first and second openings 22a and 22b having the same diameters. In general, however, only one of the portions A and B is brought into focus to expose the resist film 22.
If the portion A is brought into focus, the second opening 22b is incompletely defined in the portion B, as shown in FIG. 20. If the portion B is brought into focus, on the other hand, the first opening 22a is too much increased in diameter in the portion A, as shown in FIG. 21.
Referring again to FIG. 18, the first and second openings 22a and 22b differ in sectional form from each other for the aforementioned reason. When the second interlayer insulating film 10 is etched through the resist film 22 having such a sectional form, a second via hole 10b is incompletely defined as shown in FIG. 22, although a first via hole 10a is completely defined. Due to such incomplete opening of the second via hole 10b, a second aluminum interconnection layer 12 is not electrically connected with the pattern 9b of the first aluminum interconnection layer.
With layer multiplication of the interconnection structure, the aforementioned problem has remarkably arisen as the step is increased, due to the irregular surface of the interlayer insulating film.